| US 7,547,973 B2 | ||
| Tamper-resistant semiconductor device | ||
| Noriaki Matsuno, Hyogo (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Feb. 15, 2006, as Appl. No. 11/354,331. | ||
| Claims priority of application No. 2005-039823 (JP), filed on Feb. 16, 2005. | ||
| Prior Publication US 2006/0180939 A1, Aug. 17, 2006 | ||
| Int. Cl. H01L 23/52 (2006.01); H01L 23/48 (2006.01); H01L 29/40 (2006.01) | ||
| U.S. Cl. 257—773 [257/E23.142; 257/211; 257/679; 257/758; 326/8; 438/253] | 13 Claims |
| 1. A semiconductor device comprising:
one unit or a plurality of units of first defensive wiring provided above a diffusion isolation layer formed in a substrate
or a well;
a plurality of signal wiring layers formed above the first defensive wiring;
means for applying a predetermined signal to the first defensive wiring, monitoring an electrical or physical property of
the defensive wiring, capturing a change in the electrical or physical property of the first defensive wiring, and outputting
a control signal in response to said change for preventing fraudulent analysis and information tampering of the semiconductor
device;
one unit or a plurality of units of second defensive wiring provided above the plurality of signal wiring layers; and
means for applying a predetermined signal to the second defensive wiring and capturing a change in an electrical or physical
property of the second defensive wiring,
wherein the first defensive wiring is formed in the lowermost metal wiring layer.
|