| US 7,547,925 B2 | ||
| Superlattice strain relief layer for semiconductor devices | ||
| William S. Wong, San Carlos, Calif. (US); Michael A. Kneissl, Berlin (Germany); Zhihong Yang, Sunnyvale, Calif. (US); Mark Teepe, Menlo Park, Calif. (US); and Cliff Knollenberg, Mountain View, Calif. (US) | ||
| Assigned to Palo Alto Research Center Incorporated, Palo Alto, Calif. (US) | ||
| Filed on Feb. 17, 2006, as Appl. No. 11/356,769. | ||
| Claims priority of provisional application 60/736362, filed on Nov. 14, 2005. | ||
| Claims priority of provisional application 60/736531, filed on Nov. 14, 2005. | ||
| Prior Publication US 2007/0108456 A1, May 17, 2007 | ||
| Int. Cl. H01L 27/15 (2006.01) | ||
| U.S. Cl. 257—103 [257/79; 257/E33.032] | 6 Claims |
| 1. A semiconductor light emitting diode structure, comprising:
a substrate;
a template layer formed over and in contact with said substrate;
a superlattice structure formed over and in contact with said template layer, said superlattice structure comprising:
a plurality of layer pairs, a first layer of said layer pairs being AlN and a second layer of said layer pairs being GaN:
and
a light emitting multiple quantum well heterostructure of a composition including at least 25% aluminum, formed over said
superlattice structure.
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