| US 7,547,607 B2 | ||
| Methods of fabricating integrated circuit capacitors using a dry etching process | ||
| Kwang-jin Moon, Gyeonggi-do (Korea, Republic of); Gil-Heyun Choi, Gyeonggi-do (Korea, Republic of); Sang-Woo Lee, Seoul (Korea, Republic of); and Jae-Hwa Park, Gyeonggi-do (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Jul. 07, 2005, as Appl. No. 11/176,519. | ||
| Claims priority of application No. 10-2004-0061424 (KR), filed on Aug. 04, 2004. | ||
| Prior Publication US 2006/0030116 A1, Feb. 09, 2006 | ||
| Int. Cl. H01L 21/20 (2006.01) | ||
| U.S. Cl. 438—386 [438/399; 438/255; 438/649; 438/664; 438/682; 257/307; 257/308; 257/309] | 10 Claims |
| 1. A method of fabricating an integrated circuit capacitor, the method comprising:
forming a first metal layer on a conductive plug in an interlayer insulating layer on a substrate;
siliciding at least a portion of the first metal layer to form a metal silicide layer and a remaining first metal layer on
the conductive plug;
substantially removing the remaining first metal layer using a dry etching process such that at least a portion thereof remains;
nitrifying the portion of the remaining first metal layer; and then
forming a lower electrode comprising a second metal layer on the metal silicide layer.
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