| US 7,529,634 B2 | ||
| Method, apparatus, and computer program of searching for clustering faults in semiconductor device manufacturing | ||
| Kunihiro Mitsutake, Kanagawa-ken (Japan); and Yukihiro Ushiku, Kanagawa-ken (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Dec. 01, 2004, as Appl. No. 10/999,938. | ||
| Application 10/999938 is a division of application No. 09/931916, filed on Aug. 20, 2001, granted, now 6,885,950. | ||
| Claims priority of application No. P2000-249718 (JP), filed on Aug. 21, 2000; and application No. P2001-65338 (JP), filed on Mar. 08, 2001. | ||
| Prior Publication US 2005/0097481 A1, May 05, 2005 | ||
| Int. Cl. G01R 31/00 (2006.01) | ||
| U.S. Cl. 702—58 [438/17] | 3 Claims |
| 1. A method of optimizing a number of redundant circuits, comprising:
entering the number of redundant circuits required to repair faults in chips divided from a wafer;
calculating a frequency distribution of the redundant circuits on the chips;
calculating a number of acceptable chips produced from the wafer based on a set number of the redundant circuits using the
frequency distribution, each of the acceptable chips being defined as a chip having the redundant circuits whose number is
equal to or less than the set number of the redundant circuits; and
calculating an optimum number of redundant circuits that maximizes the number of acceptable chips produced from the wafer
according to a relationship between the number of the redundant circuits and the number of acceptable chips produced from
the wafer.
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