| US 7,529,130 B2 | ||
| Semiconductor memory device | ||
| Haruki Toda, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Mar. 27, 2006, as Appl. No. 11/389,252. | ||
| Claims priority of application No. 2005-118535 (JP), filed on Apr. 15, 2005. | ||
| Prior Publication US 2006/0239073 A1, Oct. 26, 2006 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 16/06 (2006.01) | ||
| U.S. Cl. 365—185.12 [365/185.03; 365/185.17] | 20 Claims |

| 1. A semiconductor memory device comprising:
a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; and
a sense amplifier circuit configured to read out data of the memory cell array, wherein
a plurality of information cells, in each of which one of M(M≧2) threshold levels is written, and at least one reference cell,
in which a reference threshold level is written, are defined in the memory cell array,
at the data reading, a read voltage applied to the information cell is set to be equal to or near a verify-read voltage for
verifying an m-th higher threshold level (m is equal to 1 or a natural number from 1 to M−1) in M threshold levels written
into the information cell while a reference read voltage applied to the reference cell is set to be higher than a verify-read
voltage for verifying the reference threshold level written into the reference cell by a predetermined level, and the predetermined
level is lower than a difference between a verify-read voltage for verifying an m+1-th higher threshold level written into
the information cell and the read voltage, and
the sense amplifier circuit detects a cell current difference between information cell currents generated by sequentially
applying various read voltages to the information cell and a fixed reference current generated by applying the reference read
voltage to the reference cell selected simultaneously in the memory cell array to sense data defined by the M threshold levels
of the information cell.
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