| US 7,529,120 B2 | ||
| Semiconductor memory with resistance change element | ||
| Kenji Tsuchida, Kawasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jul. 06, 2006, as Appl. No. 11/480,848. | ||
| Claims priority of application No. 2006-127760 (JP), filed on May 01, 2006. | ||
| Prior Publication US 2007/0253237 A1, Nov. 01, 2007 | ||
| Int. Cl. G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—158 [365/200; 365/196; 365/189.04; 365/189.07] | 8 Claims |
| 1. A semiconductor memory comprising:
a memory cell as a resistance change element and a switching element which are connected in series;
a read word line connected to a control terminal of the switching element;
a circuit which executes an auto-close operation for causing the read word line to be subjected to non-activation automatically
after a fixed period from start of a read operation;
a redundancy cell; and
a redundancy circuit which outputs a hit signal to select one of the memory cell and the redundancy cell,
wherein the hit signal is not reset by the auto-close operation.
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