| US 7,529,114 B2 | ||
| Semiconductor memory device | ||
| Yoshiaki Asao, Sagamihara (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Sep. 26, 2007, as Appl. No. 11/861,878. | ||
| Claims priority of application No. 2006-272056 (JP), filed on Oct. 03, 2006. | ||
| Prior Publication US 2008/0239782 A1, Oct. 02, 2008 | ||
| Int. Cl. G11C 5/06 (2006.01); G11C 11/00 (2006.01); G11C 11/14 (2006.01) | ||
| U.S. Cl. 365—63 [365/51; 365/148; 365/158; 365/163; 365/171] | 20 Claims |
| 1. A semiconductor memory device comprising:
a semiconductor substrate;
a bit line which is provided above the semiconductor substrate and runs in a first direction;
a source line which is provided above the semiconductor substrate and runs in the first direction;
an active area which is provided in the semiconductor substrate and extends in the first direction;
a first selection transistor and a second selection transistor which are formed on the active area and share a source region
electrically connected to the source line;
a first memory element having one end electrically connected to a drain region of the first selection transistor and the other
end electrically connected to the bit line; and
a second memory element having one end electrically connected to a drain region of the second selection transistor and the
other end electrically connected to the bit line,
wherein the source line includes a first interconnection portion and a second interconnection portion which run in the first
direction and are adjacent to the bit line in a second direction perpendicular to the first direction, and a third interconnection
portion which connects the first interconnection portion to the second interconnection portion and is electrically connected
to the source region.
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