| US 7,528,758 B2 | ||
| Flash-type analog to digital conversion circuit for comparing an analog input voltage with a plurality of reference voltages | ||
| Hirotomo Ishii, Kamakura (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, (Japan) | ||
| Filed on Aug. 01, 2007, as Appl. No. 11/831,958. | ||
| Application 11/831958 is a continuation of application No. 11/387242, filed on Mar. 22, 2006, granted, now 7,265,701. | ||
| Claims priority of application No. 2005-088176 (JP), filed on Mar. 25, 2005. | ||
| Prior Publication US 2007/0279275 A1, Dec. 06, 2007 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H03M 1/36 (2006.01) | ||
| U.S. Cl. 341—159 [365/226; 327/68; 329/304] | 20 Claims |
| 1. An analog to digital conversion circuit comprising:
a reference voltage generation circuit which generates a plurality of reference voltages;
a plurality of comparators which is supplied with an analog input voltage and two reference voltages out of said plurality
of reference voltages, said plurality of comparators setting a threshold voltage equivalently to a value in between the two
reference voltages in accordance with the two reference voltages, and comparing the analog input voltage with the threshold
voltage; and
an encoder circuit which is connected to said plurality of comparators and which is supplied with a plurality of comparison
output signals of said plurality of comparators and which outputs digital signals corresponding to said plurality of comparison
output signals.
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