| US 7,528,642 B2 | ||
| Semiconductor integrated circuit device and method of outputting signals on semiconductor integrated circuit | ||
| Takeshi Ishigaki, Tokyo (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Appl. No. 10/586,951 PCT Filed Aug. 15, 2005, PCT No. PCT/JP2005/015173 § 371(c)(1), (2), (4) Date Jul. 25, 2006, PCT Pub. No. WO2006/100792, PCT Pub. Date Sep. 28, 2006. |
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| Prior Publication US 2007/0296471 A1, Dec. 27, 2007 | ||
| Int. Cl. G06F 1/04 (2006.01); H03K 3/00 (2006.01) | ||
| U.S. Cl. 327—293 [327/291; 327/565] | 4 Claims |
| 1. A semiconductor integrated circuit device comprising:
a semiconductor substrate having a first area and a second area;
a plurality of counters one of which is provided in the first area and the second area and which cyclically count a same value
at a same timing in synchronism with a first clock signal and output a counter signal as a result of counting;
a first clock circuit provided in the first area, supplied with a first counter signal from the one of the counters in the
first area and outputting a second clock signal having a phase which becomes zero every time the first counter signal counts
n times (n being a natural number);
a first circuit provided in the first area and operating in synchronism with the second clock signal;
a second clock circuit provided in the second area, supplied with a second counter signal from the one of the counters in
the second area and outputting a third clock signal having a phase which becomes zero every time the second counter signal
counts m times (m being a natural number different from n); and
a second circuit provided in the second area, operating in synchronism with the third clock signal and supplying the first
circuit with data when the first and second counter signals have a value equal to a common multiple of n and m.
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