| US 7,528,569 B2 | ||
| Inverter circuit free from power-source-voltage fluctuation | ||
| Kenichiro Hidaka, Chita-gun (Japan); Hisashi Kameya, Kariya (Japan); Mitsutomo Iwase, Obu (Japan); Yasuo Ito, Nagoya (Japan); Masahiro Miyata, Kariya (Japan); and Takahiro Kojo, Gotenba (Japan) | ||
| Assigned to Denso Corporation, Kariya, Aichi-Pref (Japan); and Toyota Jidosha Kabushiki Kaisha, Toyota, Aichi-Pref (Japan) | ||
| Filed on Sep. 01, 2006, as Appl. No. 11/514,346. | ||
| Claims priority of application No. 2005-255380 (JP), filed on Sep. 02, 2005. | ||
| Prior Publication US 2007/0052384 A1, Mar. 08, 2007 | ||
| Int. Cl. H02P 27/04 (2006.01) | ||
| U.S. Cl. 318—801 [318/802; 318/807; 318/803; 318/811] | 15 Claims |
| 1. An inverter circuit comprising:
an inverter, including a plurality of pairs of a high-side switching element and a low-side switching element that are connected
in series with each other to form a pair of input terminals connected with positive and negative terminals of a dc power source,
for providing ac output power at a plurality of output terminals;
a command signal processing section for providing a command signal to set a prescribed amount of the ac output power;
a pulse generating section for generating pulse signals for controlling said inverter according to the command signal to turn
on or off with timing that includes a dead time to prevent short circuiting the dc power source, whereby said inverter has
a dead zone of operation; and
a command signal compensation section for modifying the command signal according to changes in the dc power source voltage
level to thereby control a level of the dead zone to a preset level corresponding to that which would be expected for a predetermined
constant dc power source voltage level.
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