| US 7,528,489 B2 | ||
| Semiconductor apparatus and manufacturing method | ||
| Ryouichi Kajiwara, Hitachi (Japan); Kazutoshi Itou, Hitachi (Japan); Hidemasa Kagii, Takasaki (Japan); Hiroi Oka, Tamamura (Japan); and Hiroyuki Nakamura, Maebashi (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
| Filed on Jan. 04, 2006, as Appl. No. 11/324,315. | ||
| Claims priority of application No. 2005-002016 (JP), filed on Jan. 07, 2005. | ||
| Prior Publication US 2006/0151889 A1, Jul. 13, 2006 | ||
| Int. Cl. H01L 35/08 (2006.01) | ||
| U.S. Cl. 257—772 [257/712; 420/560] | 11 Claims |
| 1. A semiconductor apparatus characterized by comprising:
a semiconductor device having a main surface, a back surface opposite to the main surface, an electrode formed on the main
surface, an electrode formed on the back surface, and a circuit formed on the main surface;
a conductive die pad to be joined to the electrode of the back surface of the semiconductor device;
a conductive lead to be electrically connected to the electrode of the main surface of the semiconductor device;
an encapsulant to encapsulate the semiconductor device, the die pad and a part of the lead; and
a means for reducing thermal stress, which means is disposed between the semiconductor device and the die pad and which is
lower in thermal expansion, lower in yield stress or lower in elastic modulus than a main material forming the die pad;
wherein the semiconductor device and the means for reducing thermal stress are joined by a joint material of a Pb free solder
alloy having Sn—Sb—Ag—Cu as its main constituent elements, having a solidus temperature not lower than 270° C. and a liquidus
temperature not higher than 400° C.
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