| US 7,528,452 B2 | ||
| Semiconductor memory | ||
| Kikuko Sugimae, Yokohama (Japan); Satoshi Tanaka, Kawasaki (Japan); Koji Hashimoto, Yokohama (Japan); and Masayuki Ichige, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on May 10, 2005, as Appl. No. 11/125,274. | ||
| Claims priority of application No. 2004-295268 (JP), filed on Oct. 07, 2004. | ||
| Prior Publication US 2006/0077702 A1, Apr. 13, 2006 | ||
| Int. Cl. H01L 27/088 (2006.01) | ||
| U.S. Cl. 257—390 [257/443] | 11 Claims |
| 8. A semiconductor memory comprising:
a plurality of bit lines that extend on a memory cell array along the column length of the memory cell array;
a plurality of word lines orthogonal to the bit lines and extending along the row length of the memory cell array; and
via contacts that are linearly arranged on the bit lines along the row length sandwiching a defective pattern region of the
bit lines at ends of the bit lines, wherein the bit lines have a stripe-shaped non-uniform pattern running along the column
length.
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