| US 7,528,447 B2 | ||
| Non-volatile semiconductor memory and method for controlling a non-volatile semiconductor memory | ||
| Toshiyuki Enda, Zushi (Japan); Hiroyoshi Tanimoto, Yokohama (Japan); Naoki Kusunoki, Fuchu (Japan); Nobutoshi Aoki, Yokohama (Japan); Fumitaka Arai, Yokohama (Japan); and Riichiro Shirota, Fujisawa (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Apr. 05, 2006, as Appl. No. 11/396,507. | ||
| Claims priority of application No. P2005-110373 (JP), filed on Apr. 06, 2005; and application No. P2005-115013 (JP), filed on Apr. 12, 2005. | ||
| Prior Publication US 2006/0237706 A1, Oct. 26, 2006 | ||
| Int. Cl. H01L 27/01 (2006.01); H01L 27/12 (2006.01); H01L 31/0392 (2006.01) | ||
| U.S. Cl. 257—347 [257/348; 257/349; 257/350; 257/351; 257/352; 257/353; 257/354; 257/E29.287] | 14 Claims |
| 1. A non-volatile semiconductor memory comprising:
a buried insulating layer;
a plurality of memory cell transistors provided in a column direction, each of the memory cell transistors comprising a channel
region having a first conductivity type and in contact with the buried insulating layer;
a first select gate transistor coupled with a first end of a arrangement of the plurality of memory cell transistors, the
first select gate transistor comprising:
a channel region in contact with the buried insulating layer and having a second conductivity type; and
a source region in contact with the buried insulating layer and having the first conductivity type;
a source line contact region electrically connected to the channel region of the first select gate transistor and having an
impurity concentration of the second conductivity type that is higher than the channel region of the first select gate transistor;
and
a source line contact plug electrically connected to the source region and the source line contact region.
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