| US 7,521,995 B1 | ||
| Inverted doherty amplifier with increased off-state impedence | ||
| Enver Krvavac, Lake Zurich, Ill. (US) | ||
| Assigned to Motorola, Inc., Schaumburg, Ill. (US) | ||
| Filed on Sep. 28, 2007, as Appl. No. 11/863,429. | ||
| Int. Cl. H03F 3/68 (2006.01) | ||
| U.S. Cl. 330—124R [330/53; 330/295; 330/302] | 9 Claims |
| 1. A power amplifier for amplifying an input signal and providing an amplified signal to a load at a summing node, wherein
the load has a first impedance value, the power amplifier comprising:
a splitter network receiving the input signal and providing a phase delayed signal and an undelayed signal, wherein the phase
delayed signal is delayed by substantially a first predetermined degree of phase delay with respect to the undelayed signal;
a carrier amplifier path amplifying the phase delayed signal and comprising a carrier amplifier and a first output match network
coupled between the carrier amplifier and the summing node; and
a peaking amplifier path amplifying the undelayed signal and comprising a peaking amplifier, a second output match network
coupled to the peaking amplifier, and a phase delay element coupled between the second output match network and the summing
node, wherein the phase delay element provides substantially the first predetermined degree of phase delay and has a designed
characteristic impedance value that is larger than the first impedance value for increasing the off-state impedance of the
peaking amplifier based on the designed characteristic impedance value, when the peaking amplifier is off.
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