	US 7,519,340 B2
	Method and apparatus capable of mitigating third order inter-modulation distortion in electronic circuits
Nicolaas Du Toit, Doylestown, Pa. (US)
Assigned to Paratek Microwave, Inc., Columbia, Md. (US)
Filed on Jan. 17, 2006, as Appl. No. 11/333,743.
Application 11/333743 is a continuation in part of application No. 11/193739, filed on Jul. 29, 2005, granted, now 7,379,711.
Claims priority of provisional application 60/592654, filed on Jul. 30, 2004.
Prior Publication US 2006/0264194 A1, Nov. 23, 2006
This patent is subject to a terminal disclaimer.
Int. Cl. H04B 17/00 (2006.01); H04B 1/10 (2006.01)

U.S. Cl. 455—130 [455/67.13; 455/295; 455/296]

4 Claims

1. A method of mitigating third order inter-modulation distortion in electronic circuits, comprising:

estimating an IP3 of said circuits using an empirical equation which includes at least one or more of the factors IP3˜IP3o−20 log Q+10 log F+10 log C−17.3 log k dBm and optimizing one or more of said factors such that the third order inter-modulation distortion is mitigated; and

wherein IP3o is related to the second and higher order derivatives of a C=f(V) function of a Varactor such that when these derivatives are reduced or tend towards zero, IP3o is increased or tends to infinity thereby optimizing IP3o.