| US 7,518,993 B1 | ||
| Prioritizing resource utilization in multi-thread computing system | ||
| Jack B. Dennis, Belmont, Mass. (US) | ||
| Assigned to The United States of America as represented by the Secretary of the Navy, Washington, D.C. (US) | ||
| Filed on Nov. 17, 2000, as Appl. No. 9/715,778. | ||
| Claims priority of provisional application 60/166685, filed on Nov. 19, 1999. | ||
| Int. Cl. H04L 12/16 (2006.01) | ||
| U.S. Cl. 370—235 [712/205; 718/102] | 30 Claims |
| 1. An apparatus comprising:
a processor capable of simultaneous execution of two or more threads of instructions, wherein the processor comprises:
at least two resource units, each capable of being assigned to an instruction of each of the threads, wherein each of the
resource units is configured to implement only a subset of instruction types of an instruction set;
a priority register to store thread information for the threads, the thread information including a priority code corresponding
to the instructions of each thread, at least one of the threads requesting use of one of the resource units for processing
a current instruction; and
a priority selector coupled to the priority register to generate an assignment signal to assign the resource units to the
requesting thread's current instruction according to the priority codes.
|