| US 7,518,921 B2 | ||
| Semiconductor memory device which includes memory cell having charge accumulation layer and control gate | ||
| Hiroshi Maejima, Milpitas, Calif. (US); and Makoto Hamada, Mountain View, Calif. (US) | ||
| Assigned to Kabushiki Kaish Toshiba, Tokyo (Japan) | ||
| Filed on Mar. 20, 2007, as Appl. No. 11/688,481. | ||
| Prior Publication US 2008/0232183 A1, Sep. 25, 2008 | ||
| Int. Cl. G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.17 [365/185.23] | 30 Claims |
| 1. A semiconductor memory device comprising:
memory cell units in which a plurality of memory cells are connected in series, the memory cells including a charge accumulation
layer and a control gate formed on the charge accumulation layer;
a memory cell array in which the memory cell units are disposed;
a word line which is connected to the control gates of the memory cells;
a bit line which is electrically connected to drains of the memory cells positioned on one end sides of the memory cell units;
a source line which is electrically connected to sources of the memory cells positioned on the other end sides of the memory
cell units;
a sense amplifier which amplifies data read from the memory cell onto the bit line;
a row decoder which selects the word line; and
a source line driver circuit which is arranged in the row decoder and applies a first voltage to the source line, the source
line driver being controlled by control signals independent of control of the row decoder.
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