| US 7,518,646 B2 | ||
| Image sensor ADC and CDS per column | ||
| Jeffrey J. Zarnowski, McGraw, N.Y. (US); Ketan V. Karia, Cortland, N.Y. (US); and Thomas Poonnen, Cortland, N.Y. (US) | ||
| Assigned to Panavision Imaging LLC, Homer, N.Y. (US) | ||
| Filed on Sep. 20, 2005, as Appl. No. 11/230,385. | ||
| Application 11/230385 is a continuation in part of application No. 10/106399, filed on Mar. 25, 2002, granted, now 6,965,407. | ||
| Claims priority of provisional application 60/278639, filed on Mar. 26, 2001. | ||
| Prior Publication US 2006/0012696 A1, Jan. 19, 2006 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H04N 3/14 (2006.01); H04N 5/335 (2006.01) | ||
| U.S. Cl. 348—302 [348/294; 250/208.1] | 15 Claims |
| 1. Arrangement for converting analog pixel values from an array of pixels to a digital video signal, said array comprising
a plurality of columns and at least one row, each column having at one pixel therein, and each column providing a respective
pixel value; the arrangement comprising
a source of clock signals;
an N-bit counter coupled to said source of clock signals;
an N-bit DAC connected to said counter and having a ramp output providing a signal corresponding to a count existing on said
counter;
a plurality of digital counter/latch elements each associated with a respective one of said columns and each also coupled
to said source of clock signals;
a plurality of comparators each associated with a respective one of said columns, and having one input connected to receive
the respective column pixel value, another input connected to the ramp output of said N-bit counter, and a comparator output
connected to a gating terminal of the respective digital counter/latch element;
a video readout bus; and
means selectively transferring contents of said digital counter/latch elements to said video output bus to produce said digital
video signal.
|