a semiconductor substrate having source/drain regions, and a channel region located between the source/drain regions;

a gate insulating film disposed on the channel region of the semiconductor substrate;

a gate electrode disposed on the gate insulating film, the gate electrode comprising a polycrystalline silicon (polysilicon) layer, an ohmic layer, a barrier layer, and a metal layer disposed one atop the other in the foregoing sequence, and wherein the gate electrode has recesses in both sides thereof adjacent sides of the barrier layer;

a hard mask disposed on the gate electrode; and

first spacers extending over sides of the hard mask, the metal layer, the barrier layer, and the ohmic layer, and over side portions of the sides of the polycrystalline silicon layer, respectively.