| US 7,518,189 B1 | ||
| Independently-double-gated field effect transistor | ||
| Douglas R. Hackler, Sr., Boise, Id. (US); and Stephen A. Parke, Nampa, Id. (US) | ||
| Assigned to American Semiconductor, Inc., Boise, Id. (US) | ||
| Filed on Feb. 25, 2006, as Appl. No. 11/307,863. | ||
| Application 11/307863 is a continuation in part of application No. 10/613169, filed on Jul. 03, 2003, granted, now 7,015,547. | ||
| Int. Cl. H01L 29/94 (2006.01) | ||
| U.S. Cl. 257—347 [257/134] | 29 Claims |
| 1. A field effect transistor, comprising:
a substrate;
a substrate dielectric disposed on the substrate;
a bottom gate disposed on the substrate dielectric;
a source disposed above the substrate dielectric and having a source extension extending from a main body of the source to
be adjacent to the bottom gate;
a drain disposed above the substrate dielectric and having a drain extension extending from a main body of the drain to be
adjacent to the bottom gate;
a channel confined by being coupled between the source extension and the drain extension, the channel making a junction contact
to the bottom gate to form a JFET;
a top gate disposed above the channel;
a local interconnect coupled to the top gate;
a first insulating spacer disposed between the top gate and the source; and
a second insulating spacer disposed between the top gate and the drain.
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