a p-type MIS transistor having a first gate electrode including silicon doped with p-type impurities;

an n-type MIS transistor having a second gate electrode including silicon doped with n-type impurities; and

a first shared line made of metal, a second shared line made of silicon of which a top portion is silicided, and a third shared line made of metal, each line connecting the p-type MIS transistor and the n-type MIS transistor and serving as a path of a power supply current or a ground current, wherein

the first gate electrode and the second gate electrode have silicided top portions, respectively, to establish electrical connection therebetween,

the second shared line is formed only on an isolation region provided in a semiconductor substrate, and is connected to the first and third shared lines formed on an interlayer insulating film, respectively via a contact plug,

the silicon, positioning at a lower doped portion of the second shared line, has a p-type region made of p-type polysilicon doped at least with p-type impurities, and

the p-type region of the second shared line has a line width larger than the line widths of the first gate electrode and the second gate electrode.