| US 7,517,638 B2 | ||
| Method of manufacturing a semiconductor apparatus with a tapered aperture pattern to form a predetermined line width | ||
| Fumikatsu Uesawa, Kanagawa (Japan) | ||
| Assigned to Sony Corporation, Tokyo (Japan) | ||
| Filed on Mar. 02, 2005, as Appl. No. 11/70,461. | ||
| Application 11/070461 is a continuation of application No. 10/720851, filed on Nov. 24, 2003, granted, now 6,953,746. | ||
| Application 10/720851 is a continuation of application No. 10/154237, filed on May 23, 2002, granted, now 6,716,747. | ||
| Claims priority of application No. 2001-153326 (JP), filed on May 23, 2001. | ||
| Prior Publication US 2005/0176257 A1, Aug. 11, 2005 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G03F 7/00 (2006.01) | ||
| U.S. Cl. 430—311 [430/313; 430/317; 430/322; 430/323] | 19 Claims |
| 1. A method of manufacturing a semiconductor apparatus comprising:
providing a film to be processed on a substrate, wherein the film to be processed has a varying thickness and the substrate
has a uniform thickness;
providing a first dielectric mask material film on said film to be processed, the first dielectric mask material film having
a dielectric constant lower than silicon dioxide and a heatproof temperature of about 350 degrees Centigrade;
forming a second mask on the first dielectric mask material;
providing a resist film on the second dielectric mask material film;
forming a first vertical aperture pattern on said resist film;
using said resist film as a mask;
etching said first dielectric mask material film to form an open pattern using the mask, said open pattern being formed with
tapered sides such that a bottom of said open pattern is narrower than a first vertical aperture pattern side of said open
pattern; and
forming a second vertical aperture pattern in said film to be processed by etching said film to be processed,
wherein the bottom of the open pattern is formed at a desirable micro dimension exceeding capabilities of lithography techniques.
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