	US 7,490,230 B2
	Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor
Michael Gottlieb Jensen, Cambridgeshire (United Kingdom); and Soumya Banerjee, San Jose, Calif. (US)
Assigned to MIPS Technologies, Inc., Mountain View, Calif. (US)
Filed on Mar. 22, 2005, as Appl. No. 11/87,063.
Prior Publication US 2006/0179276 A1, Aug. 10, 2006
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/50 (2006.01)

U.S. Cl. 712—245 [718/103]

37 Claims

1. An apparatus for selecting one of N fetch addresses associated with N corresponding threads for providing to an instruction cache for fetching instructions therefrom in a multithreading microprocessor that concurrently executes the N threads, wherein a subset of the N threads may request to fetch instructions in a selection cycle, the apparatus comprising:

a first input, for receiving a first corresponding N-bit value specifying which of the N threads was last selected to fetch instructions, wherein only one of said N bits of said first value corresponding to said last selected thread is true;

a second input, for receiving a second corresponding N-bit value, each of said N bits of said second value being false if said corresponding one of the N threads is requesting to fetch instructions;

a barrel incrementer, coupled to said first and second inputs, configured to add said second value to a 1-bit left-rotated version of said first value to generate a sum and a carry-out bit, wherein said barrel incrementer includes said carry-out bit as a carry-in bit of the add to generate the sum; and

combinational logic, coupled to said barrel incrementer, configured to generate a third corresponding N-bit value specifying which of the N threads is selected next to fetch instructions, said third value comprising a Boolean AND of said sum and an inverted version of said second value, wherein only one of said N bits of said third value corresponding to said next selected one of the N threads is true.