| US 7,489,743 B2 | ||
| Recovery circuits and methods for the same | ||
| Hwa Su Koh, Seongnam-si (Korea, Republic of); Ki Mio Ueda, Seoul (Korea, Republic of); Duck Hyun Chang, Seongnam-si (Korea, Republic of); Nyun Tae Kim, Yongin-si (Korea, Republic of); and Dae Seung Jeong, Seoul (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (Korea, Republic of) | ||
| Filed on Jul. 13, 2005, as Appl. No. 11/179,558. | ||
| Claims priority of application No. 10-2004-0054824 (KR), filed on Jul. 14, 2004. | ||
| Prior Publication US 2006/0013349 A1, Jan. 19, 2006 | ||
| Int. Cl. H03D 3/18 (2006.01) | ||
| U.S. Cl. 375—327 | 29 Claims |
| 1. A recovery circuit comprising:
a phase detector configured to compare a phase of input data with a phase of a current output clock to generate a first up
signal and a first down signal,
a quadrant decision unit configured to determine a phase location for the current output clock and output quadrant decision
signals based on a voltage difference between first and second phase control voltages,
a quadrant controller configured to output a second up signal and a second down signal based on the first up signal and the
first down signal and the quadrant decision signals,
a charge pump unit configured to output the first and second phase control voltages based on the second up signal and the
second down signal, and
a phase interpolator configured to select clocks from a plurality of clocks based on the quadrant decision signals and output
an output clock based on the selected clocks and the first and second phase control voltages.
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