| 1. A memory device comprising:
a V-shaped phase change layer pattern disposed on a substrate, the V-shaped phase change layer pattern having a sharp tip
that is closer to the substrate than remaining portions of the V-shaped phase change layer pattern, a portion of the V-shaped
phase change layer pattern remote from the sharp tip including an etch stop layer and a pattern interlayer insulating layer
stacked thereon; and
a support interlayer insulating layer disposed between the etch stop layer and the semiconductor substrate and including therein
a lower contact hole, the lower contact hole including therein a contact hole spacer and a lower contact hole node, wherein
a portion of the V-shaped phase change layer pattern that is adjacent the sharp tip contacts the lower contact hole node,
and wherein the etch stop layer comprises an insulating layer having an etching ratio different from the pattern interlayer
insulating layer.
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