US 7,488,981 B2
Memory devices having sharp-tipped phase change layer patterns
Won-Cheol Jeong, Seoul (Korea, Republic of); Hyeong-Jun Kim, Seoul (Korea, Republic of); Jae-Hyun Park, Gyeonggi-do (Korea, Republic of); and Chang-Wook Jeong, Seoul (Korea, Republic of)
Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of)
Filed on Dec. 21, 2004, as Appl. No. 11/18,643.
Claims priority of application No. 10-2003-0100470 (KR), filed on Dec. 30, 2003.
Prior Publication US 2005/0139816 A1, Jun. 30, 2005
Int. Cl. H01L 27/108 (2006.01); H01L 29/00 (2006.01); H01L 31/036 (2006.01); H01L 31/112 (2006.01)
U.S. Cl. 257—68  [257/E29.17; 257/69] 26 Claims
OG exemplary drawing
 
1. A memory device comprising:
a V-shaped phase change layer pattern disposed on a substrate, the V-shaped phase change layer pattern having a sharp tip that is closer to the substrate than remaining portions of the V-shaped phase change layer pattern, a portion of the V-shaped phase change layer pattern remote from the sharp tip including an etch stop layer and a pattern interlayer insulating layer stacked thereon; and
a support interlayer insulating layer disposed between the etch stop layer and the semiconductor substrate and including therein a lower contact hole, the lower contact hole including therein a contact hole spacer and a lower contact hole node, wherein a portion of the V-shaped phase change layer pattern that is adjacent the sharp tip contacts the lower contact hole node, and wherein the etch stop layer comprises an insulating layer having an etching ratio different from the pattern interlayer insulating layer.