| US 7,488,628 B2 | ||
| Methods for fabricating ferroelectric memory devices with improved ferroelectric properties | ||
| Yoon-Jong Song, Seoul (Korea, Republic of); Nak-Won Jang, Seoul (Korea, Republic of); and Ki-Nam Kim, Gyeonggi-do (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Mar. 20, 2006, as Appl. No. 11/384,689. | ||
| Application 11/384689 is a division of application No. 10/775016, filed on Feb. 10, 2004, granted, now 7,045,839. | ||
| Claims priority of application No. 2003-08202 (KR), filed on Feb. 10, 2003. | ||
| Prior Publication US 2006/0160252 A1, Jul. 20, 2006 | ||
| Int. Cl. H01L 21/00 (2006.01); H01L 21/335 (2006.01); H01L 21/8232 (2006.01); H01L 21/8242 (2006.01) | ||
| U.S. Cl. 438—142 [438/3; 438/240; 438/239; 438/253] | 17 Claims |
| 1. A method of fabricating a ferroelectric memory device, the method comprising:
forming a transistor on a semiconductor substrate;
forming a first interlayer dielectric on the semiconductor substrate and on the transistor;
forming a buried plug that penetrates the first interlayer dielectric;
forming a bottom electrode of a capacitor on the buried plug and the first interlayer dielectric;
forming a third interlayer dielectric on the first interlayer dielectric;
removing a top part of the third interlayer dielectric;
forming a reaction buffer layer on the third interlayer dielectric so that the side surfaces of the bottom electrode of the
capacitor are covered by the reaction buffer layer;
forming a capacitor-ferroelectric layer on the reaction buffer layer and the bottom electrode; and
forming a top electrode of the capacitor on the capacitor-ferroelectric layer.
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