| US 7,483,933 B2 | ||
| Correlation architecture for use in software-defined radio systems | ||
| Yan Wang, Plano, Tex. (US); Eran Pisek, Plano, Tex. (US); and Jasmin Oz, Plano, Tex. (US) | ||
| Assigned to Samsung Electronics Co., Ltd., Suwon-si (Korea, Republic of) | ||
| Filed on Jun. 10, 2005, as Appl. No. 11/150,511. | ||
| Application 11/150511 is a continuation in part of application No. 11/123313, filed on May 06, 2005. | ||
| Claims priority of provisional application 60/653968, filed on Feb. 17, 2005. | ||
| Claims priority of provisional application 60/654035, filed on Feb. 17, 2005. | ||
| Prior Publication US 2006/0184599 A1, Aug. 17, 2006 | ||
| Int. Cl. G06F 17/15 (2006.01); G06F 7/52 (2006.01) | ||
| U.S. Cl. 708—422 [708/622] | 20 Claims |
| 1. A re-configurable correlation unit for correlating a sequence of chip samples, said re-configurable correlation unit comprising:
a memory for storing said sequence of chip samples;
a plurality of add-subtract cells, wherein each of said add-subtract cells is capable of receiving a plurality of real bits,
a, from a first chip sample in said memory and a plurality of imaginary bits, b, from said first chip sample; and
a processing unit comprising:
a plurality of sign select units, each of said plurality of sign select units capable of receiving from one of said plurality
of add-subtract cells a first input equal to a sum (a+b) of said plurality of real bits, a, and said plurality of imaginary
bits, b, and a second input equal to a difference (a−b) of said plurality of real bits, a, and said plurality of imaginary
bits, b, and wherein said each sign select unit generates a real output and an imaginary output, wherein each of said real
output and said imaginary output is equal to one of: 1) said sum (a+b) multiplied by one of +1 and −1 and 2) said difference
(a−b) multiplied by one of +1 and −1.
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