| US 7,482,204 B2 | ||
| Chip packaging process | ||
| Chin-Li Kao, Penghu County (Taiwan); Yi-Shao Lai, Taipei County (Taiwan); Jeng-Da Wu, Kaohsiung (Taiwan); and Tong-Hong Wang, Selangor D. E. (Malaysia) | ||
| Assigned to Advanced Semiconductor Engineering, Inc., Kaohsiung (Taiwan) | ||
| Filed on Dec. 21, 2007, as Appl. No. 11/962,109. | ||
| Application 11/962109 is a division of application No. 10/907340, filed on Mar. 30, 2005, granted, now 7,335,982. | ||
| Claims priority of application No. 93109186 A (TW), filed on Apr. 02, 2004. | ||
| Prior Publication US 2008/0096325 A1, Apr. 24, 2008 | ||
| Int. Cl. H01L 21/44 (2006.01) | ||
| U.S. Cl. 438—122 [257/E23.101; 438/106] | 8 Claims |
| 1. A chip packaging process, comprising:
forming a cavity on a heat sink;
forming a first encapsulant at the bottom of the cavity, wherein the first encapsulant is in contact with sidewalls of the
cavity;
disposing a circuit substrate on the heat sink, wherein the circuit substrate has an opening that corresponds in position
to the cavity;
disposing a chip on the first encapsulant;
electrically connecting the chip and the circuit substrate;
forming a second encapsulant over the first encapsulant to encapsulate the chip and a portion of the circuit substrate; and
forming a plurality of conductive bumps on the circuit substrate.
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