| US 7,475,369 B1 | ||
| Eliminate false passing of circuit verification through automatic detecting of over-constraining in formal verification | ||
| William K. Lam, Newark, Calif. (US); and Shrenik M. Mehta, San Jose, Calif. (US) | ||
| Assigned to Sun Microsystems, Inc., Santa Clara, Calif. (US) | ||
| Filed on Mar. 18, 2005, as Appl. No. 11/83,805. | ||
| Int. Cl. G06F 17/50 (2006.01); G06F 9/45 (2006.01) | ||
| U.S. Cl. 716—5 [716/4; 716/18; 703/13; 703/14] | 10 Claims |
| 1. A method for determining whether a potential constraint set for a circuit under test (CUT) overconstrains inputs that can
be applied to the CUT, the method comprising:
allowing a user to describe a potential constraint set for the CUT, wherein the potential constraint set specifies inputs
that the user believes can be applied to the CUT by an environment circuit during operation;
establishing, based upon the potential constraint set, a set of conditions for the environment circuit, wherein the set of
conditions sets forth limitations on what outputs are expected to be generated by the environment circuit during operation;
applying a set of environmental inputs to the environment circuit to produce a set of environmental outputs;
determining whether the set of environmental outputs violate the set of conditions; and
in response to a determination that the set of environmental outputs violate the set of conditions, concluding that the potential
constraint set overconstrains inputs that can be applied to the CUT.
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