| US 7,475,316 B2 | ||
| System, method and storage medium for providing a high speed test interface to a memory subsystem | ||
| Thomas M. Cowell, Poughkeepsie, N.Y. (US); Kevin C. Gower, LaGrangeville, N.Y. (US); and Frank LaPietra, Poughquag, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Jan. 09, 2008, as Appl. No. 11/971,578. | ||
| Application 11/971578 is a continuation of application No. 10/977790, filed on Oct. 29, 2004, granted, now 7,395,476. | ||
| Prior Publication US 2008/0104290 A1, May 01, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G01R 31/28 (2006.01); G11C 29/00 (2006.01); G11C 7/00 (2006.01); G06F 13/00 (2006.01) | ||
| U.S. Cl. 714—734 [714/718; 710/71; 365/201] | 19 Claims |
| 1. A buffer device for testing a memory subsystem, the buffer device comprising:
a parallel bus port adapted for connection to a slow speed bus;
a serial bus port adapted for connection to a high speed bus, wherein the high speed bus operates at a faster speed than the
slow speed bus; and
a bus converter having a standard operating mode for converting serial packetized input data received via the serial bus port
into parallel bus output data for output via the parallel bus port and an alternate operating mode for converting parallel
bus input data received via the parallel bus port into serial packetized output data for output via the serial bus port, wherein
the serial packetized input data is consistent in function and timing to the serial packetized output data.
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