| US 7,475,306 B2 | ||
| Scan test method, integrated circuit, and scan test circuit | ||
| Hideki Hamada, Kanagawa (Japan) | ||
| Assigned to NEC Electronics Corporation, Kanagawa (Japan) | ||
| Filed on Oct. 28, 2004, as Appl. No. 10/974,741. | ||
| Claims priority of application No. 2003-368620 (JP), filed on Oct. 29, 2003. | ||
| Prior Publication US 2005/0097415 A1, May 05, 2005 | ||
| Int. Cl. G01R 31/28 (2006.01); G06F 11/00 (2006.01) | ||
| U.S. Cl. 714—726 [714/736] | 14 Claims |
| 1. A scan test method of an integrated circuit including a combinational circuit, there being a flip-flop coupled to an input
of the combination circuit and a flip-flop coupled to an output of the combination circuit, said flip-flops forming a scan
chain, comprising:
setting initial test values to the flip-flops forming the scan chain;
performing a first capture operation whereby a first output of the combination circuit is captured by said flip-flop coupled
to the output of the combination circuit;
performing a feedback shift operation feeding said first output of the scan chain back to an input side of the scan chain
for re-input during a shift operation in the scan chain;
performing a second capture operation, whereby a second output of the combination circuit based on inputting said first output
to said combination circuit is captured by said flip-flop coupled to the output of the combination circuit; and
comparing said second output of the scan chain, output after performing the second capture operation, with an expected value.
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