| US 7,475,232 B2 | ||
| Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines | ||
| Christopher Michael Abernathy, Austin, Tex. (US); Jonathan James Dement, Austin, Tex. (US); Ronald Hall, Cedar Park, Tex. (US); and Albert James Van Norstrand, Round Rock, Tex. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Jul. 19, 2005, as Appl. No. 11/184,349. | ||
| Prior Publication US 2007/0022278 A1, Jan. 25, 2007 | ||
| Int. Cl. G06F 9/00 (2006.01) | ||
| U.S. Cl. 712—244 | 10 Claims |
| 1. A method for improving the performance of an in-order processor comprising the steps of:
detecting an exception at or before a completion point for an execution pipeline, wherein said execution pipeline comprises
a backup pipeline and a regular pipeline, wherein said backup pipeline stores a copy of instructions issued to said regular
pipeline, and wherein the backup pipeline and the regular pipeline have an equal number of pipeline stages;
asserting an upper stall point to prevent instructions from entering said backup pipeline and said regular pipeline prior
to said flushing of instructions younger than said instruction causing said exception in said regular pipeline;
asserting a lower stall point to prevent instructions from flowing out of said backup pipeline prior to said flushing of instructions
younger than said instruction causing said exception in said regular pipeline;
flushing instructions younger than an instruction causing said exception in said regular pipeline;
handling said detected exception;
de-asserting said lower stall point to allow instructions to flow from said backup pipeline to said regular pipeline; and
allowing instructions to flow from said backup pipeline to said regular pipeline.
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