| US 7,474,722 B1 | ||
| Systems and methods for sample rate conversion using multiple rate estimate counters | ||
| Daniel L. W. Chieng, Austin, Tex. (US); Jack B. Andersen, Austin, Tex. (US); and Larry E. Hand, Meridian, Miss. (US) | ||
| Assigned to D2Audio Corporation, Austin, Tex. (US) | ||
| Filed on Mar. 19, 2004, as Appl. No. 10/805,591. | ||
| Claims priority of provisional application 60/469725, filed on May 12, 2003. | ||
| Claims priority of provisional application 60/456414, filed on Mar. 21, 2003. | ||
| Claims priority of provisional application 60/456430, filed on Mar. 21, 2003. | ||
| Claims priority of provisional application 60/456429, filed on Mar. 21, 2003. | ||
| Claims priority of provisional application 60/456421, filed on Mar. 21, 2003. | ||
| Claims priority of provisional application 60/456422, filed on Mar. 21, 2003. | ||
| Claims priority of provisional application 60/456428, filed on Mar. 21, 2003. | ||
| Claims priority of provisional application 60/456420, filed on Mar. 21, 2003. | ||
| Claims priority of provisional application 60/456427, filed on Mar. 21, 2003. | ||
| Int. Cl. H04L 7/00 (2006.01) | ||
| U.S. Cl. 375—355 | 18 Claims |
| 1. A system comprising:
a clock source;
a first counter coupled to receive a clock signal from the clock source and configured to count cycles of the clock signal
in a sample period corresponding to a first digital data stream;
a second counter coupled to receive the clock signal from the clock source and configured to count cycles of the clock signal
in a sample period corresponding to a second digital data stream; and
a data processor coupled to the first and second counters and configured to
read a first number of cycles counted by the first counter and a second number of cycles counted by the second counter, and
convert at least one of the first and second digital data streams from a corresponding input sample rate to a predetermined
sample rate based on the number of cycles counted in the corresponding digital data stream,
wherein the first counter is configured to count cycles corresponding to the first digital data stream by incrementing once
for each cycle after a frame sync signal is received in the first digital data stream and wherein the second counter is configured
to count cycles corresponding to the second digital data stream by incrementing once for each cycle after a frame sync signal
is received in the second digital data stream.
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