US 7,474,386 B2
Wafer flatness evaluation method, wafer flatness evaluation apparatus carrying out the evaluation method, wafer manufacturing method using the evaluation method, wafer quality assurance method using the evaluation method, semiconductor device manufacturing method using the evaluation method and semiconductor device manufacturing method using a wafer evaluated by the evaluation method
Tadahito Fujisawa, Tokyo (Japan); Soichi Inoue, Yokohama (Japan); Makoto Kobayashi, Nishishirakawa-gun (Japan); Masashi Ichikawa, Nishishirakawa-gun (Japan); Tsuneyuki Hagiwara, Tokyo (Japan); and Kenichi Kodama, Mito (Japan)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan); Shin-Etsu Handotai Co., Ltd., Tokyo (Japan); and Nikon Corporation, Tokyo (Japan)
Filed on Feb. 26, 2007, as Appl. No. 11/710,552.
Application 11/710552 is a division of application No. 10/739275, filed on Dec. 19, 2003, granted, now 7,230,680.
Claims priority of application No. 2002-370502 (JP), filed on Dec. 20, 2002.
Prior Publication US 2007/0177127 A1, Aug. 02, 2007
This patent is subject to a terminal disclaimer.
Int. Cl. G03B 27/58 (2006.01); G03B 27/32 (2006.01); G03B 27/52 (2006.01)
U.S. Cl. 355—77  [355/55; 355/72] 12 Claims
OG exemplary drawing
 
1. A wafer manufacturing method comprising:
acquiring a wafer from an ingot based on a working process condition set;
measuring front and rear surface shapes of the acquired wafer;
dividing the front surface of the wafer into sites, selecting a flatness calculating method according to a predetermined factor to be evaluated and acquiring flatness in the wafer surface;
determining whether or not the acquired flatness in the wafer surface satisfies a requirement from a budget;
fixing the set working process condition when the flatness in the wafer surface satisfies the requirement from the budget; and
changing the set working process condition when the flatness in the wafer surface does not satisfy the requirement from the budget.