| US 7,474,005 B2 | ||
| Microelectronic element chips | ||
| Vladimir Anatolyevich Aksyuk, Westfield, N.J. (US); Nagesh R Basavanhally, Skillman, N.J. (US); Avinoam Kornblit, Highland Park, N.J. (US); Warren Yiu-Cho Lai, Chatham Township, N.J. (US); Joseph Ashley Taylor, Springfield, N.J. (US); and Robert Francis Fullowan, Berkley Heights, N.J. (US) | ||
| Assigned to Alcatel-Lucent USA Inc., Murray Hill, N.J. (US) | ||
| Filed on May 31, 2006, as Appl. No. 11/445,072. | ||
| Prior Publication US 2007/0278699 A1, Dec. 06, 2007 | ||
| Int. Cl. H01L 23/52 (2006.01); H01L 23/48 (2006.01); H01L 29/40 (2006.01) | ||
| U.S. Cl. 257—777 [257/E27.161; 257/685; 257/686; 257/778; 437/209; 437/902; 438/108] | 14 Claims |
| 1. An apparatus, comprising:
a chip substrate having a first chip surface facing away from a second chip surface;
an array of microelectronic elements on the first chip surface, each of the microelectronic
elements being a member of at least one of the following classes: semiconductor devices,
passive filters, sensors, and optoelectronic devices; and
an array of conductors each in communication with one of the microelectronic elements, each of the conductors passing from
a first point on the chip surface at the one of the microelectronic elements, entirely within the chip substrate to a second
point on the second chip surface at an under bump metallization pad, wherein the distance within the chip substrate between
the first and second points is less than about 150 micrometers.
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