| US 7,473,633 B2 | ||
| Method for making integrated circuit chip having carbon nanotube composite interconnection vias | ||
| Toshiharu Furukawa, Essex Junction, Vt. (US); Mark Charles Hakey, Fairfax, Vt. (US); David Vaclav Horak, Essex Junction, Vt. (US); Charles William Koburger, III, Delmar, N.Y. (US); Mark Eliot Masters, Essex Junction, Vt. (US); Peter H Mitchell, Jericho, Vt. (US); and Stanislav Polonsky, Putnam Valley, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Jul. 20, 2006, as Appl. No. 11/458,726. | ||
| Application 11/458726 is a division of application No. 10/787640, filed on Feb. 26, 2004, granted, now 7,135,773. | ||
| Prior Publication US 2006/0292861 A1, Dec. 28, 2006 | ||
| Int. Cl. H01L 21/4763 (2006.01) | ||
| U.S. Cl. 438—622 [438/627; 438/648; 438/687; 257/E51.04] | 18 Claims |
| 1. A method of making an integrated circuit chip, comprising the steps of:
providing a first chip layer having a plurality of electrical contacts for coupling to electrical conductors in a second chip
layer;
forming a dielectric layer over said first chip layer, said dielectric layer having a plurality of cavities corresponding
to respective electrical contacts of said plurality of electrical contacts in said first chip layer;
growing a plurality of carbon nanotubes in each of said plurality of cavities, said step of growing a plurality of carbon
nanotubes leaving voids within each said cavity between said carbon nanotubes;
filling substantially all of the volume of said voids throughout the length of each said cavity with a conductive metal to
form a respective electrically conductive via in each said cavity, each said electrically conductive via forming a respective
portion of a respective electrical logic circuit path to one or more of a plurality of active devices of said integrated circuit
chip; and
forming said second chip layer over said dielectric layer.
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