| US 7,473,589 B2 | ||
| Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same | ||
| Erh Kun Lai, Taichung (Taiwan); Hang-Ting Lue, Hsinchu (Taiwan); and Kuang Yeu Hsieh, Hsinchu (Taiwan) | ||
| Assigned to Macronix International Co., Ltd., Hsinchu (Taiwan) | ||
| Filed on Oct. 13, 2006, as Appl. No. 11/549,520. | ||
| Claims priority of provisional application 60/748911, filed on Dec. 09, 2005. | ||
| Prior Publication US 2007/0134876 A1, Jun. 14, 2007 | ||
| Int. Cl. H01L 21/00 (2006.01); H01L 21/84 (2006.01) | ||
| U.S. Cl. 438—149 [438/257; 257/E21.17; 257/E21.21; 257/E21.32; 257/E21.293; 257/E21.267; 257/E21.411; 257/E21.646] | 47 Claims |
| 1. A method for fabricating a non-volatile memory device comprising a plurality of bitline layers and a plurality of wordline
layers sequentially formed on top of each other, the method comprising:
forming the plurality of bitline layers layer, wherein forming each bitline layer comprises:
forming a semiconductor layer on an insulator, and
patterning and etching the semiconductor layer to form a plurality of bitlines;
forming word line layers in the plurality of wordline layers over respective preceding ones of the plurality of bitline layers,
wherein forming each wordline layer comprises:
sequentially forming a trapping structure and a conducting layer, and
patterning and etching the trapping structure and the conducting layer to form a plurality of wordlines; and
forming source/drain regions in regions of the plurality of bitlines not covered by the plurality of wordlines with active
regions in the plurality of bit lines beneath the plurality of wordlines.
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